The present invention relates to a timing recovery circuit for a receiver for pulse amplitude-modulated (PAM) signals.
Reception of a PAM signal of L discrete amplitude levels (where L is an integer equal to or greater than 2) is generally performed through the sampling of the incoming PAM signal at a proper time (point) and the subsequent determination of the amplitude level of the sampled signal. In this case, the timing signal for the determinaion of the proper sampling time is usually obtained by a self-timing method for extracting the timing signal from a reception signal in some way or other. One of such self-timing methods already known is the nonlinear extraction technique. This technique performs the extraction of a timing signal by utilizing a line spectrum appearing at the clock frequency position when a reception PAM signal is subjected to a nonlinear operation, such as a squaring operation. For this purpose, a nonlinear circuit is needed together with a bandpass filter for passing the clock frequency and an amplitude limiting circuit for eliminating the level fluctuation of said spectrum. As a result, the timing recovery circuit resorting to this technique becomes complicated. Moreover, those circuits used tend to malfunction in the high frequency region, leading to the disadvantage that the extracted timing signal is liable to contain undesirable phase noise. For example, the timing recovery circuit outlined above is shown in FIG. 18 of a paper entitled "An Experimental 560 Mbits/s Repeater with Integrated Circuits" by Engel Roza and Peter W. Millenaar, published in the IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-25, No. 9, pages 995 to 1004, September 1977 (Reference 1).
Another known self-timing method is the maximum likelihood detection technique. With this technique, a reception PAM signal is differentiated to control a timing signal generator so that timing positions may be adjusted to coincide with the zero crossings of the differentiated waveforms. This technique, employing a voltage-controlled oscillator (VCO) in place of such a nonlinear circuit as mentioned above, enables the generation of timing signals of a constant amplitude free from undesirable phase noise. However, since a differentiating circuit and a sample hold circuit for holding each sampled value of the differentiated waveforms (or the polarity signal of the sampled value) are indispensable to the second technique, the whole circuit structure eventually becomes bulky and complicated (see FIG. 4 of a paper entitled "Carrier and Bit Synchronization in Data Communication-A Tutorial Review" by L. E. Franks, published in the IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-28, No. 8, Pages 1107 to 1121, August 1980 (Reference 2)). Furthermore, because the fluctuation of a reception signal adversely affects the differentiated waveforms by the use of this technique, waveform deterioration on the transmission line must be minimized. This consequently makes the transmission system expensive.
One object of the present invention, therefore, is to provide a significantly small-scale timing recovery circuit capable of withstanding the deteriorated reception waveforms and free from the above-mentioned disadvantages unavoidable with the prior art timing recovery circuits.